Feature sizes of integrated circuits are increasingly scaled down and TSVs for 3D interconnection are also increasingly being decreased in size with continuous progress in semiconductor processes. Patterning, etching and filling processes for the TSVs encounter unprecedented challenges. Etching and filling for TSV trenches, with increased depth-to-width ratio due to scaling down thereof, are becoming increasingly difficult. Conventional etching and filling processes gradually fail to meet the industrial requirements. Consequently, there is a need for an improved TSV structure for 3D interconnection and a method for manufacturing the same, so as to meet the requirements of the technological development.